|
|
System partitioning for
SoC designs. |
|
|
Cell library development for standard cells, analog macros and memory
cells. |
|
|
Cell layout design, characterization,
and development of interfacing circuits. |
|
|
Place and route for fabrication
technologies ranging from 0.35 micron to 0.09 micron. |
|
|
Physical verification / extraction. |
