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Tata Elxsi offers modeling and ESL services for the complete life cycle of your product.ESL’s multi fold benefits include architectural exploration, fast software development and debugger implementation.Tata Elxsi’s vast reportaire of expertise and experience offer modeling solutions and support at all stages of you product’s development from algorithmic realization level to cycle accurate representation of the complete system.
Algorithmic model :
To verify a component or system’s adherence to the functional specification, its algorithmic model is implemented
Architectural Exploration :
Along with meeting the functional specification, architecture exploration of a system is done for system performance analysis, power estimation and design decisions on buses, memories etc. This helps in achieving first time silicon success. Timed, untimed or partially timed representations of the system can be modeled depending on the requirements.
Software development :
Software development correctness can be achieved only when run on target platform. Several iterations of debugging and validating would be required to arrive at final, optimal solution.
Conventionally, hardware solutions such as emulators or FPGAs were considered. However these issues are two-fold –
- Late availability in the process chain
- Hardware errors could be detected
Simulators, however, can be made ready after the design and specifications are freezed. Parallelly, software development activities can be started and can be validated on the simulator.
Additional features such as “profile” will aide in algorithmic analysis and performance estimation resulting in a stronger design.
Hence all the software development activities like device drivers, firmware, embedded software, OS, applications that were conventionally validated on the board can be validated on the system model
IDE development :
Full fledged Integrated Development Environment (IDE) with various debugging capabilities can be ready at the same time as the silicon, re-using the models . IDE will help the end users of the silicon to compile and debug their application specific software.
Verification :
RTL models are analyzed by using various test scenarios which can be run on the C-models of the corresponding modules. The C-models can not only be used for developing the reference outputs of test scenarios it can also be reused to conduct functional verifications of the RTL models for analyzing and verifying the design behavior
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Thus, simulator helps in reducing the time-to-market factor to a large extent by helping in
Higher chances of first time silicon success
• Validate hardware and software before silicon is available
Earlier software development
• Validate all software before tapeout
Simultaneously, providing Credible architecture
• Optimized performance and power analysis
• Choosing the most feasible architecture from various alternatives
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• ARM based cycle accurate simulators.
• Xtensa based configurable multiprocessor transaction level simulator using OCP compliant SONIC MXC system bus.
• Cycle accurate modeling for network processor.
• Development of Instruction Set Simulator. Debugger development.
• ESL tools for simulator development: SoC Designer from ARM.
• FlexRay IP: Transaction level Model for FlexRay protocol in SystemC.
• Graphical user interfaces for SDK, Emulators, debuggers .
• Maintainance, support and renovation of legacy development tools like
compilers, simulators, debuggers.
• A team of 50 competent engineers who have undergone the life cycle process of a complete project on multiple platforms. |
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Languages
• SystemC , ANSI C, C++
• Java, Visual Basic
• System Verilog, Specman e
• Verilog, VHDL
• Scripting languages
Tools
• Modelsim, VCSim
• GTK Viewer
• Specman
• Sonics studio
• ARM SOCDesigner, RVDS
• Eclipse
• Xtensa Xplorer
• Code composer Studio, IAR
• VSS, Clearcase, CVS
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Processors
• ARM
• Xtensa
• PIC series
• MSP430
• TI DSPs
Peripherals
• FlexRay
• CAN, LIN, SPI, mibSPI
• ADC, CRC
• Timers ,GPIO
• DMA controller
• Interrupt Controllers
• Bus protocol converters
• Memory controllers
• Memories (RAM, Flash)
• Clock Modules
• JPEG, ISI
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• Complete simulator development life-cycle support from architecture exploration to final chip system simulator that can validate end applications.
• System simulation environment at
- Transaction level modeling
- Functional/ Behavioral modeling
- Cycle accurate modeling
- Pin accurate modeling
• OSCI TLM 2.0 expertise.
• Models of product prototype designs on different platforms.
• Designs based on configurable processors [Tensilica] .
• HDL to C/C++/SystemC conversions.
• Design expertise of several person-years with leading companies.
• Tailored process for model design and development.
• IP SystemC models.
• User interface for FPGA board/ emulators.
• FlexRay IP: Transaction level Model for FlexRay protocol in SystemC
• JPEG TLM 2 model following OSCI standards
• Proven FlexRay IP integration into customer specific system
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